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E2E1031-27-Y4
Semiconductor MSM66589/66P589/66Q589
Semiconductor OLMS-66K Series CMOS 16-Bit Microcontroller
el im This version: Jan. 1998 MSM66589/66P589/66Q589 ina ry Previous version: Nov. 1996
Pr
GENERAL DESCRIPTION
The MSM66589/66P589/66Q589 is a high-speed, high-performance 16-bit microcontroller that employs OKI original nX-8/500S CPU core. The MSM66589/66P589/66Q589 includes a 16-bit CPU, ROM, RAM, a 10-bit A/D converter, serial ports, flexible timers, pulse-width modulator (PWM), and I/O ports. The MSM66Q589 is a Flash EEPROM version.
FEATURES
* Program memory space Internal ROM : : : : : 128K bytes 96K bytes (MSM66589/66P589) 128K bytes (MSM66Q589) 64K bytes 4K bytes
* Data memory space Internal RAM * High-speed execution Minimum instruction execution time : 100 nsec (@ 20 MHz) * Built-in multiplier * Powerful instruction set : Instruction set superior in orthogonal matrix 8/16-bit data transfer instructions 8/16-bit arithmetic instructions Multiplication and division operation instructions Bit manipulation instructions Bit logic instructions ROM table reference instructions * Abundant addressing modes : Register addressing Page addressing Pointing register indirect addressing Stack addressing Immediate addressing * I/O port Analog input only ports : 16 channels Input-output ports : 11 ports 8 bits, 1 port 6 bits (Each bit can be configured to be an input or output) * Flexible timers Free run counters : 19 bits 1, 16 bits 1 19-bit CAP with a divider :4 16-bit double buffer RTO :6 16-bit RTO/PWM :2 16-bit CAP/RTO :6 * 8-bit general timer :1 8-bit event counter :1 * 16-bit PWM :8 Input clock divider :1 * 8-bit serial ports
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Semiconductor
MSM66589/66P589/66Q589
UART mode with BRG :1 Synchronous/UART switchable mode with BRG :1 * 10-bit A/D converter : 16 channels * Transition detector :6 * Watchdog timer :1 * Interrupts Non-maskable :1 Maskable : Internal 47/external 2 (4-level priority can be set) * ROM window function * Standby modes HALT mode STOP mode * Package: 128-pin plastic QFP (QFP128-P-2828-BK) (Product name: MSM66589-GS-BK) (Product name: MSM66P589-GS-BK) (Product name: MSM66Q589GS-BK) indicates the code number.
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P2_0/RTO4
P2_5/RTO9 P2_6/FTM10 P3_0/FTM11A P3_1/FTM11B CPU Core Control Registers RAM 4K bytes PSW PC TSR CSR ROM * 96K bytes ALU Instruction Decoder ALU Control ACC Memory Control Pointing R. Local R. SSP LRB EA ALE/P5_5 PSEN/P5_4 RD/P7_1 WR/P7_0 WAIT/P7_2 AD0/P0_0 AD7/P0_7 A8/P1_0 A15/P1_7 A16/P9_0
BLOCK DIAGRAM
Semiconductor
P3_3/FTM11D P3_4/CAP0
Flexible Timer
P3_7/CAP3 P10_0/RTO12 P10_1/RTO13 P10_2/FTM14
BUS PORT CONTROL
P10_5/FTM17 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 P6_6/RXD0 P6_7/TXD0
Serial Port
P7_4/PWM0
P8_3/PWM7
PWM
AVDD VREF AGND AI0
A/ D Converter
AI15
P4_0/ETMCK P4_1/ECTCK
Event Timer
P4_2/TRNS0
P4_7/TRNS5
Transition Detector System Control Port Control
P6_0/INT0 P6_1/INT1 NMI O S C 0
Interrupt O E P P P P P P P PPPPP 012345678911 01
P7_3/CLKOUT
Peripheral
O S C 1
R E S
WDT
MSM66589/66P589/66Q589
3/27
*
MSM66Q589 (Flash EEPROM version) contains 128K bytes Flash EEPROM.

PIN CONFIGURATION (TOP VIEW)
Semiconductor
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 TRNS2/P4_4 TRNS1/P4_3 TRNS0/P4_2 ECTCK/P4_1 ETMCK/P4_0 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 VDD CAP3/P3_7 CAP2/P3_6 CAP1/P3_5 CAP0/P3_4 FTM11D/P3_3 FTM11C/P3_2 FTM11B/P3_1 FTM11A/P3_0 GND P10_7 P10_6 FTM17/P10_5 FTM16/P10_4 FTM15/P10_3 FTM14/P10_2 RTO13/P10_1 RTO12/P10_0 P2_7
TRNS3/P4_5 TRNS4/P4_6 TRNS5/P4_7 P5_0 P5_1 P5_2 P5_3 NMI RES EA VDD AVDD VREF AI0 AI1 AI2 AI3 AI4 AI5 AI6 AI7 AI8 AI9 AI10 AI11 AI12 AI13 AI14 AI15 AGND GND INT0/P6_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P6_1/INT1 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 P6_6/RXD0 P6_7/TXD0 GND OSC0 OSC1 P5_5/ALE P5_4/PSEN P7_0/WR P7_1/RD P7_2/WAIT P7_3/CLKOUT P7_4/PWM0 P7_5/PWM1 P7_6/PWM2 P7_7/PWM3 VDD P8_0/PWM4 P8_1/PWM5 P8_2/PWM6 P8_3/PWM7 P8_4 P8_5 P8_6 P8_7 GND OE P0_0/AD0
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128-Pin Plastic QFP (FLAT)
MSM66589/66P589/66Q589
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P2_6/FTM10 P2_5/RTO9 P2_4/RTO8 P2_3/RTO7 P2_2/RTO6 P2_1/RTO5 P2_0/RTO4 VDD P9_7 P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0/A16 P1_7/A15 P1_6/A14 P1_5/A13 P1_4/A12 P1_3/A11 P1_2/A10 P1_1/A9 P1_0/A8 GND P0_7/AD7 P0_6/AD6 P0_5/AD5 P0_4/AD4 P0_3/AD3 P0_2/AD2 P0_1/AD1
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Semiconductor
MSM66589/66P589/66Q589
PIN DESCRIPTION
Symbol P0_0-P0_7/ AD0-AD7 P1_0-P1_7/ A8-A15 P2_0-P2_5/ RTO4-RTO9 P2_6/FTM10 P2_7 P3_0-P3_3/ FTM11A-FTM11D P3_4-P3_7/ CAP0-CAP3 P4_0/ETMCK P4_1/ECTCK P4_2-P4_7/ TRNS0-TRNS5 P5_0-P5_3 P5_4/PSEN P5_5/ALE Type I/O Description P0: 8-bit input-output port. Each bit can be assigned to be an input or an output. AD: When an external memory is used, these pins output the lower 8 bits of the address. These pins also input or output the data. P1: 8-bit input-output port. Each bit can be assigned to input or output. A: When an external memory is used, these pins output the upper 8 bits of the address. P2: 8-bit input-output port. Each bit can be assigned to input or output. RTO: Output pin for real time output FTM10: Capture input pin or real-time output pin P3: 8-bit input-output port. Each bit can be assigned to input or output. FTM11A: Capture input pin or real-time output pin FTM11B-D: 4-port real-time output pin CAP : Capture input pin P4: 8-bit input-output port. Each bit can be assigned to input or output. ETMCK: External clock input pin of 8-bit general timer ECTCK: External clock input pin of 8-bit event counter TRNS: Transition detector input pin P5: 6-bit input-output port. Each bit can be assigned to input or output. PSEN: Strobe pulse output pin to fetch to external program memory ALE: Timing pulse output pin to latch the lower 8 bits of the address output from port 0 when the CPU accesses the external memory P6: 8-bit input-output port. Each bit can be assigned to input or output. INT0, 1: External interrupt request input pin RXD1 : SCI1 Receiver data input pin TXD1 : SCI1 Transmitter data output pin RXC1 : SCI1 Receiver circuit clock pin TXC1 : SCI1 Transmitter circuit clock pin RXD0 : SCI0 Receiver data input pin TXD0 : SCI0 Transmitter data output pin P7: 8-bit input-output port. Each bit can be assigned to input or output. WR: Write strobe output pin for external data memory RD: Read strobe output pin for external data memory WAIT: CPU wait request input pin when accessing external data memory CLKOUT: Output pin to output clock pulse specified by PRPHF PWM: PWM output pin P8: 8-bit input-output port. Each bit can be assigned to input or output. PWM: PWM output pin P9: 8-bit input-output port. Each bit can be assigned to input or output. A16: When an external program memory is used, this pin outputs the MSB of the address. P10: 8-bit input-output port. Each bit can be assigned to input or output. RTO: Output pin for real time output. FTM: Capture input pin or real-time output pin
I/O
I/O
I/O
I/O
I/O
P6_0/INT0 P6_1/INT1 P6_2/RXD1 P6_3/TXD1 P6_4/RXC1 P6_5/TXC1 P6_6/RXD0 P6_7/TXD0 P7_0/WR P7_1/RD P7_2/WAIT P7_3/CLKOUT P7_4-P7_7/ PWM0-PWM3 P8_0-P8_3/ PWM4-PWM7 P8_4-P8_7 P9_0/A16 P9_1-P9_7
I/O
I/O
I/O
I/O
P10_0-P10_1/ RTO12-RTO13 P10_2-P10_5/ FTM14-FTM17 P10_6-P10_7 P11_0-P11_7
I/O
I/O
P11: 8-bit input-output port. Each bit can be assigned to input or output.
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Semiconductor
MSM66589/66P589/66Q589
PIN DESCRIPTION (Continued)
Symbol AI0-AI15 AVDD VREF AGND OSC0 OSC1 Type I I I I I Basic clock oscillation pin O When P0, P1, P2, P7_4-P7_7, and P8-P11 are in an output state and OE pin is "H" level, P0, P1, P2, P7_4-P7_7, and P8-P11 go to a high-impedance state. When P0, P1, P2, P7_4-P7_7, and P8-P11 are in an output state and OE pin is "L" level, P0, P1, P2, P7_4-P7_7, and P8-P11 output "H" or "L" level. However, when P0, P1, P2, P7_4-P7_7, and P8-P11 are in an input state, these ports are not under the influence of OE pin. Nonmaskable interrupt request input pin Low-active RESET input pin Normally set to "H" level. If set to "L" level, the program memory goes into external access mode and accesses external program memory Power supply pin Ground pin Description Analog signal input pin for A/D converter Power supply input pin for A/D converter Reference voltage input pin for A/D converter GND input pin for A/D converter
OE
I
NMI RES EA VDD GND
I I I I I
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Semiconductor
MSM66589/66P589/66Q589
REGISTERS
Accumulator Control Register (CR) Program Status Word
15 ACC 0
15 PSW
0
Bit 15 : Carry flag (CY) Bit 14 : Zero flag (ZF) Bit 13 : Half carry flag (HC) Bit 12 : Data descriptor (DD) Bit 11 : Sign flag (S) Bit 10 : Master interrupt priority flag (MIP) Bit 9 : Overflow flag (OV) Bit 8 : Master interrupt enable flag (MIE) Bit 7 : Multiply and accumulate operation bank flag (MAB)* Bit 6 : User flag (F1) Bit 5 : Bank common base (BCB1)* Bit 4 : Bank common base (BCB0)* Bit 3 : User flag (F0) Bit 2-0 : System control base 2-0 (SCB2-0) * Bit 7 (MAB), Bit 5 (BCB1), and Bit 4 (BCB0) can be used as the User flag. 15 0 PC LRB SSP
7 CSR TSR 0
Program Counter Local Register Base System Stack Pointer Segment Register Code Segment Register Table Segment Register Pointing Register (PR)
15
0
Index Register 1 Index Register 2 Data pointer User Stack Pointer
X1 X2 DP USP
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Semiconductor Local Register
ER0 ER1 ER2 ER3 7 R1 R3 R5 R7 07
MSM66589/66P589/66Q589
0 R0 R2 R4 R6
8/27
Semiconductor
MSM66589/66P589/66Q589
SFR
Address [H] 0000 0001 0002 0003 0004 0005 0006 0007 00086 0009 000A 000B 000C6 000D6 000E 000F6 0010 0011 0012 0013 0014 00156 0016 0017 0018 0019 001A 001B 001C 001D6 001E 001F 0020 0021 0022 0023 0024 00256 00266 0027 ROM Window Register ROM Ready Control Register RAM Ready Control Register Stop Code Acceptor Standby Control Register Port 0 Data Register Port 1 Data Register Port 2 Data Register Port 3 Data Register Port 4 Data Register Port 5 Data Register Port 6 Data Register Port 7 Data Register Port 0 Mode Register Port 1 Mode Register Port 2 Mode Register Port 3 Mode Register Port 4 Mode Register Port 5 Mode Register Port 6 Mode Register Port 7 Mode Register Port 8 Data Register Port 9 Data Register Port 10 Data Register Port 11 Data Register TRNS Control Register Transition Detector Watchdog Timer ROMWIN ROMRDY RAMRDY STPACP SBYCON P0 P1 P2 P3 P4 P5 P6 P7 P0IO P1IO P2IO P3IO P4IO P5IO P6IO P7IO P8 P9 P10 P11 -- -- TRNSIT WDT -- -- -- -- -- P0P1 P2P3 P4P5 P6P7 P0P1IO 8/16 P2P3IO P4P5IO P6P7IO P8P9 P10P11 TRNSCON -- -- W 16 8 R/W W R/W 8 00 FF FF "0" C8 00 00 00 00 00 C0 00 00 00 00 00 00 00 C0 00 00 00 00 00 00 F000 C0 Stop Name System Stack Pointer Local Register Base Program Status Word Accumulator Table Segment Register Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation -- LRBL LRBH PSWL PSWH ACCL ACCH TSR SSP LRB PSW ACC -- 8 R/W 8/16 16 Reset Status FFFF Undefined 00 00 00 00 00
6 mark in the address column indicates that there is a nonexistent bit in its register.
9/27
Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Address [H] 0028 0029 002A 002B 002C6 002D6 002E 002F 0030 0031 00326 0033 0034 00356 0036 0037 00386 00396 003A6 003B 003C 003D 003E 003F 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F Interrupt Request Flag Disable Register 0 Interrupt Request Flag Disable Register1 Interrupt Request Register 0 Interrupt Request Register 1 Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Control Register 00 Interrupt Priority Control Register 01 Interrupt Priority Control Register 10 Interrupt Priority Control Register 11 IRQD0L IRQD0H IRQD1L IRQD1H IRQ0L IRQ0H IRQ1L IRQ1H IE0L IE0H IE1L IE1H IP00L IP00H IP01L IP01H IP10L IP10H IP11L IP11H IRQD0 IRQD1 IRQ0 IRQ1 IE0 IE1 IP00 IP01 IP10 IP11 R/W 8/16 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Port 1 Secondary Function Control Register Port 2 Secondary Function Control Register Port 3 Secondary Function Control Register Port 4 Secondary Function Control Register Port 5 Secondary Function Control Register Port 6 Secondary Function Control Register Port 7 Secondary Function Control Register Port 8 Secondary Function Control Register Port 9 Secondary Function Control Register Port 10 Secondary Function Control Register
Name Port 8 Mode Register Port 9 Mode Register Port 10 Mode Register Port 11 Mode Register A/D Interrupt Control Register A/D Hardware Select Enable Register A/D Hardware Select Register
Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation P8IO P9IO P10IO P11IO ADINTCON ADHENCON -- -- P1SF P2SF P3SF P4SF P5SF P6SF P7SF P8SF P9SF P10SF P8P9IO 8/16 P10P11IO -- -- ADHSEL R/W 8 16
Reset Status 00 00 00 00 C0 F0 0000
-- -- -- -- -- -- -- -- -- --- R/W 8
00 80 00 00 CF 00 00 F0 00 00
6 mark in the address column indicates that there is a nonexistent bit in its register.
10/27
Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Address [H] 0050 0051 0052 0053 0054 0055 0056 0057 0058 0059 005A 005B 005C 005D 005E 005F 0060 0061 0062 0063 0064 0065 0066 0067 0068 0069 006A 006B 006C 006D 006E 006F 0070 0071 0072 0073 0074 0075 0076 0077 Name PWM Counter 0 PWM Counter 1 PWM Counter 2 PWM Counter 3 PWM Counter 4 PWM Counter 5 PWM Counter 6 PWM Counter 7 PWC0 Buffer Register PWC1 Buffer Register PWC2 Buffer Register PWC3 Buffer Register PWC4 Buffer Register PWC5 Buffer Register PWC6 Buffer Register PWC7 Buffer Register PWR0 Buffer Register PWR1 Buffer Register PWR2 Buffer Register PWR3 Buffer Register Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PWC0 PWC1 PWC2 PWC3 PWC4 PWC5 PWC6 PWC7 PWC0BF PWC1BF 16 PWC2BF PWC3BF PWC4BF PWC5BF PWC6BF PWC7BF PW0BF PW1BF PW2BF PW3BF R/W FFFF FFFF FFFF FFFF FFFF FFFF 0000 0000 0000 0000 R Reset Status FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
6 mark in the address column indicates that there is a nonexistent bit in its register.
11/27
Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Address [H] 0078 0079 007A 007B 007C 007D 007E 007F 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 008C 008D 008E 008F 0090 0091 0092 0093 0094 0095 0096 0097 0098 0099 009A 009B 009C 009D 009E 009F Name PWR4 Buffer Register PWR5 Buffer Register PWR6 Buffer Register PWR7 Buffer Register Timer Register 0 Timer Register 1 Timer Register 2 Timer Register 3 Timer Register 4 Timer Register 5 Timer Register 6 Timer Register 7 Timer Register 8 Timer Register 9 Timer Register 10 Timer Register 11 Timer Register 12 Timer Register 13 Timer Register 14 Timer Register 15 Abbreviated Abbreviated 8/16 R/W Name (BYTE) Name (WORD) Operation -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- PW4BF PW5BF R/W PW6BF PW7BF TMR0 TMR1 R TMR2 TMR3 TMR4 TMR5 16 TMR6 TMR7 TMR8 TMR9 R/W TMR10 TMR11 TMR12 TMR13 TMR14 TMR15 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Undefined Undefined 0000 0000 0000 0000 Undefined Undefined Reset Status 0000 0000
6 mark in the address column indicates that there is a nonexistent bit in its register.
12/27
Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Address [H] 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF 00B06 00B16 00B26 00B36 00B46 00B56 00B66 00B76 00B8 00B96 00BA6 00BB6 00BC6 00BD6 00BE6 00BF6 00C0 00C1 00C2 00C3 00C46 00C56 00C66 00C76 Name Timer Register 16 Timer Register 17 TMR4 Buffer Register TMR5 Buffer Register TMR6 Buffer Register TMR7 Buffer Register TMR12 Buffer Register TMR13 Buffer Register RTO Control Register 0 RTO Control Register 1 RTO Control Register 2 RTO Control Register 3 RTO Control Register 4 RTO Control Register 5 RTO Control Register 6 RTO Control Register 7 RTO Control Register 8 RTO Control Register 9 RTO Control Register 10 RTO Control Register 11 RTO Control Register 12 RTO Control Register 13 RTO Control Register 14 Timer Counter 0 Low-order 3 bits Timer Counter 0 Timer Counter 1 TMR0 Low-order 3 Bits TMR1 Low-order 3 Bits TMR2 Low-order 3 Bits TMR3 Low-order 3 Bits Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation -- -- -- -- -- -- -- -- RTOCON0 RTOCON1 RTOCON2 RTOCON3 RTOCON4 RTOCON5 RTOCON6 RTOCON7 RTOCON8 RTOCON9 RTOCON10 RTOCON11 RTOCON12 RTOCON13 RTOCON14 TM0L -- -- TMR0L TMR1L TMR2L TMR3L TMR16 TMR17 TMR4BF TMR5BF 16 TMR6BF TMR7BF TMR12BF TMR13BF -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TM0 16 TM1 -- -- -- -- R 8 0000 Undefined Undefined Undefined Undefined 8 R/W 0000 0000 0000 0000 F8 F8 F8 F8 FC FC F8 F8 00 F8 F8 F8 F8 F8 F8 1F 0000 Reset Status 0000 0000 0000 0000
6 mark in the address column indicates that there is a nonexistent bit in its register.
13/27
Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Address [H] 00C86 00C96 00CA6 00CB6 00CC6 00CD6 00CE6 00CF6 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00DF 00E06 00E16 00E2 00E36 00E4 00E56 00E6 00E76 00E8 00E96 00EA 00EB 00EC 00ED 00EE 00EF Name Event Dividing Counter 0 Event Dividing Counter 1 Event Dividing Counter 2 Event Dividing Counter 3 EVDV0 Buffer Register EVDV1 Buffer Register EVDV2 Buffer Register EVDV3 Buffer Register A/D Result Register 0 A/D Result Register 1 A/D Result Register 2 A/D Result Register 3 A/D Result Register 4 A/D Result Register 5 A/D Result Register 6 A/D Result Register 7 A/D Result Register 8 A/D Result Register 9 A/D Result Register 10 A/D Result Register 11 A/D Result Register 12 A/D Result Register 13 A/D Result Register 14 A/D Result Register 15 A/D Control Register L A/D Control Register H Timer Control Register TM Setting Register 2 TM Setting Register TMR Mode Register TMR Mode Register 2 Capture Control Register Capture Control Register 2 PWM RUN Register PWM Control Register 0 PWM Control Register 1 PWM Control Register 2 PWM Control Register 3 Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation EVDV0 EVDV1 EVDV2 EVDV3 EVDV0BF EVDV1BF EVDV2BF EVDV3BF ADCR0 ADCR1 ADCR2 ADCR3 ADCR4 ADCR5 ADCR6 ADCR7 ADCR8 ADCR9 ADCR10 ADCR11 ADCR12 ADCR13 ADCR14 ADCR15 ADCONL ADCONH TMCON TMSEL2 -- TMRMODE TMRMODE2 -- CAPCON2 PWRUN PWCON0 PWCON1 PWCON2 PWCON3 -- -- -- -- -- -- -- -- ADCR0W ADCR1W ADCR2W ADCR3W ADCR4W ADCR5W ADCR6W ADCR7W ADCR8W ADCR9W ADCR10W ADCR11W ADCR12W ADCR13W ADCR14W ADCR15W -- -- -- -- TMSEL -- -- CAPCON -- -- -- -- -- -- 8 R/W 16 16 8 8 80 80 00 C0 0000 00 C0 0000 00 00 00 00 00 00 R/W (*1) 8/16 (*1) Undefined R/W 8 Reset Status C0 C0 C0 C0 C0 C0 C0 C0
6 mark in the address column indicates that there is a nonexistent bit in its register.
14/27
Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Address [H] 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F86 00F9 00FA 00FB 00FC6 00FD6 00FE 00FF 0100 01016 0102 0103 0104 0105 0106 01076 01086 01096 010A 010B 010C 010D 010E 010F 0110 0111 01126 01136 01146 0115 0116 0117 SCI0 Timer SCI0 Timer Control Register SCI0 Transmit Control Register SCI0 Receive Control Register -- S0CON ST0CON SR0CON S0TM -- -- -- R/W 8 16 0000 02 8A 1A Peripheral Control Register NMI Control Register External Interrupt Control Register PRPHF NMICON EXICON -- -- -- R/W 8 (*3) FC or 7C 00 Name PWM Interrupt Register 0 PWM Interrupt Register 1 PWM Interrupt Enable Register 0 PWM Interrupt Enable Register 1
SCI0 Transmit/Receive Buffer Register
Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation PWINTQ0 PWINTQ1 PWINTE0 PWINTE1 S0BUF S0STAT S1BUF S1STAT GTMCON GEVC GTMC GTMR EVNTCONL EVNTCONH PWINTQ 8/16 PWINTE -- -- -- -- -- -- -- -- -- -- 8 R/W
Reset Status 00 00 00 00 Undefined 00 Undefined 00 30 00 00 00 88 88
SCI0 Status Register
SCI1 Transmit/Receive Buffer Register
SCI1 Status Register
General-purpose 8-bit Timer Control Register
8-bit Event Counter
General-purpose 8-bit Timer Counter General-purpose 8-bit Timer Register
Event Control Register Emulator Use Area * Note 3 Memory Size Acceptor Memory Size Control Register
MEMSACP MEMSCON
-- --
W R/W
8
"0" FC
15/27
Semiconductor
MSM66589/66P589/66Q589
SFR (Continued)
Address [H] 0118 0119 011A6 011B6 011C6 011D 011E6 011F6 0120 0121 0122 0123 0124 0125 0126 0127 6 mark in the address column indicates that there is a nonexistent bit in its register. *1 The 8/16 bit operation for the ADCR items is a special word manipulation. If a byte access is made, high-order 8 bits of the A/D Result register are accessed, and if a word access is made, the 10-bit contents of the A/D Result register are accessed. Data can be written in the even number A/D Result registers and the odd number A/D Result registers separately. When data is first written in the A/D Result register 0 (ADCR0), data is also written in other even number A/D Result registers at a time. When data is first written in the A/D Result register 1 (ADCR1), data is also written in other odd A/D Result registers at a time. *2 Do not access the emulator use area. *3 The initial values of PRPHF (SFR=107H) are as follows: At reset by RES pin: VBFF (bit 6) is "1"; CKOUT1 (bit 1) and CKOUT0 (bit 0) are "0". At reset by WDT and BRK instructions and operation code trap: VBFF (bit 6) holds the value just before reset; CKOUT1 (bit 1) and CKOUT0 (bit 0) are "0". In both cases, the OE pin status is read for OERD (bit 7). TBC Clock Dividing Counter TBC Clock Dividing Register TBCKDVC TBCKDVR -- -- R R/W 8 F0 F0 SCI1 Timer SCI1 Timer Control Register SCI1 Transmit Control Register SCI1 Receive Control Register Name Abbreviated Abbreviated R/W 8/16 Name (BYTE) Name (WORD) Operation -- S1CON ST1CON SR1C0N S1TM -- -- -- R/W 8 16 Reset Status 0000 02 88 08
16/27
Semiconductor
MSM66589/66P589/66Q589
ADDRESSING MODES
The MSM66589/66P589/66Q589 provides independent 64K-byte data and 128K-byte program spaces with various types of addressing modes. These modes are shown below for both RAM (for data space) and ROM (for program space). RAM Addressing Mode (for data space) * Register addressing
Example INC USP USP
* Page addressing a) sfr page
Example L A, sfr IRQ0 SFR 0000H 0040H
b) Fixed page
Example ST A, fix 0C0H RAM 0200H 02C0H
c) Current page
Example ROR off 078H RAM xx00H xx78H
* Direct data addressing
Example CLR dir 780H RAM 0700H 0780H
17/27
Semiconductor * Pointing register indirect addressing a) DP/X1 indirect
Example
XCHG A, [DP]
DP
b) Post increment DP indirect
Example
ADD A, [DP+]
DP After access, DP is incremented by 2.
c) Post decrement DP indirect
Example
SUB A, [DP-]
DP After access, DP is decremented by 2.
d) DP/USP indirect with 7-bit displacement
Example
AND A, 12[DP]
DP
e) X1/X2 indirect with 16-bit base
Example
XOR A, 1234H[X1] X1
f) X1 indirect with 8-bit register (A, R0) displacement
Example
OR A, [X1+A]
X1

RAM RAM RAM -64 to +63 RAM
MSM66589/66P589/66Q589
0-65535
RAM
AL
RAM
18/27
Semiconductor
* Special bit area addressing a) Fixed page SBA area (02C0H to 02FFH)
Example
SB sbafix 2D1H.3
b) Current page SBA area (C0H to FFH)
Example
RB sbaoff 2E9H.7
ROM Addressing Mode (for program space) * Immediate addressing
Example
MOV SSP, #7FFH
* Table data addressing TSR specifies the address segment. a) Direct
Example LC A, 5678H
b) RAM addressing indirect
Example
CMPC A, [USP]
USP
c) RAM addressing indirect with 16-bit base
Example LC A, 1234H[ER0] RAM ER0

RAM 02C0H 02D1H RAM C0H E9H
ROM
Address
MSM66589/66P589/66Q589
xxxxH
ROM
5678H
ROM
0-65535
ROM
19/27
Semiconductor
MSM66589/66P589/66Q589
MEMORY MAP
Program Memory Space
Segment 0 0000H Vector table area (74 bytes) 0049H 004AH 0069H 006AH VCAL table area (32 bytes) 0000H Segment 1
Internal ROM area
Internal ROM area
0FFFH 1000H ACAL area (2K bytes) 17FFH 1800H
0FFFH 1000H ACAL area (2K bytes) 17FFH 1800H
7FFFH 8000H External ROM area * FFFFH FFFFH
*
For MSM66Q589 (Flash EEPROM version), 8000H to 0FFFFH in Segment 1 are in the internal ROM area.
Data Memory Space
0000H 00FFH 0100H 01FFH 0200H 02FFH 0300H SFR Area Expanded SFR Area FIX Area Internal RAM Area Area where local register can be set 01FFH 0200H 0208H 0210H
....
Expanded SFR Area
X1 X2 DP USP X1 X2 DP USP X1 USP X1 X2 DP USP
SCB=0 SCB=1
.....
09FFH 0A00H 11FFH 1200H
Pointing Register Set
0238H 0240H External Memory Area
SCB=7
Area where ROM window can be set FFFFH
02C0H SBA Area (64 bytes) 0300H
Area where SB, RB, JBS, and JBR instructions can be performed in shorter byte count.
20/27
Semiconductor
MSM66589/66P589/66Q589
ABSOLUTE MAXIMUM RATINGS
(Ta=25C) Parameter Digital Power Supply Voltage Input Voltage Output Voltage Analog Power Supply Voltage Analog Reference Voltage Analog Input Voltage Power Dissipation Storage Temperature Symbol VDD VI VO AVDD VREF VAI PD TSTG Ta=85C Per package Per output -- GND=AGND=0 V Ta = 25C Condition Rating -0.3 to 7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to AVDD+0.3 -0.3 to VREF 855 50 -50 to +150 mW C Unit
V
RECOMMENDED OPERATING CONDITIONS
Parameter Digital Power Supply Voltage Analog Power Supply Voltage Analog Reference Voltage Analog Input Voltage Memory Hold Voltage Operating Frequency Ambient Temperature Fan Out Symbol VDD AVDD VREF VAI VDDH fOSC Ta N Condition fOSC20 MHz VDD=AVDD -- -- fOSC=0 Hz VDD=5 V10% -- MOS load TTL load P0, P5_4, P5_5, P7_0, P7_1
P1 to P11 (except P5_4,P5_5, P7_0, P7_1)
Range 4.5 to 5.5 4.5 to 5.5 AVDD-0.3 to AVDD AGND to VREF 2.0 to 5.5 0 to 20 -40 to +85 20 2 1
Unit
V
MHz C --
21/27
Semiconductor
MSM66589/66P589/66Q589
ELECTRICAL CHARACTERISTICS
DC Characteristics (Preliminary)
(VDD=5 V10%, Ta=-40 to +85C) Parameter H Level Input Voltage L Level Input Voltage H Level Output Voltage H Level Output Voltage L Level Output Voltage L Level Output Voltage Input Leakage Current Input Current Input Current H Level Output Current H Level Output Current L Level Output Current L Level Output Current Input Capacitance Output Capacitance Analog Reference Current Current Consumption (in STOP mode) Current Consumption (in HALT mode) Current Consumption 1 1 1, 4 2 1, 4 2 3, 6 5 7 1, 4 2 1, 4 2 IOH VO=2.4 V IOL ILO CI CO IREF IDDS IDDH IDD VO=VDD/0 V f=1 MHz, Ta=25C A/D in operation A/D stopped VDD=2 V, Ta=25C* * fOSC=20 MHz No load IIH/IIL VI=VDD/0 V
H Level Input Voltage 2, 4, 5, 6, 7
Symbol VIH VIL VOH VOL
Condition - - IOH=-400 mA IOH=-200 mA IOL=3.2 mA IOL=1.6 mA
Min. 2.2 0.80VDD -0.3 -0.3 VDD-0.4 VDD-0.4 - - - - - -2 -1 10 5 - - - - - - - - -
Typ. - - - - - - - - - - - - - - - - 5 7 - - 0.2 1 45 80
Max. VDD+0.3 VDD+0.3 0.8 0.2VDD - - 0.4 0.4 1/-1 1/-250 15/-15 - - - - 2 - - 6 10 10 100
Unit
L Level Input Voltage 2, 4, 5, 6, 7
V
A
mA
Output Leakage Current 1, 2, 4
A pF mA A A
mA
1. 2. 3. 4. 5. 6. 7. *
Applied to P0 Applied to P1 to P11 (except P5_4, P5_5, P7_0, P7_1) Applied to AIN Applied to P5_4, P5_5, P7_0, P7_1 Applied to RES Applied to EA, OE, NMI Applied to OSC0 Ports for input pins are VDD or GND, otherwise no load.
22/27
Semiconductor AC Characteristics (Preliminary) * External program memory control
MSM66589/66P589/66Q589
(VDD=5 V10%, Ta=-40 to +85C) Parameter Clock (OSC) pulse width ALE pulse width PSEN pulse width PSEN pulse delay time Low-order address set-up time Low-order address hold time High-order address set-up time High-order address hold time Instruction set-up time Instruction hold time Symbol toW tAW tPW tPAD tALS tALH tAHS tAPH tIS tIH CL=50 pF Condition -- Min. 25 2toW-10 2toW-10 toW-10 2toW-10 toW-10 3toW-10 Max. -- -- -- toW+10 2toW+10 toW+10 3toW+10 toW+10 -- toW-10 nsec Unit
* External data memory control
(VDD=5 V10%, Ta=-40 to +85C) Parameter Clock (OSC) pulse width ALE pulse width RD pulse width WR pulse width RD pulse delay time WR pulse delay time Low-order address set-up time Low-order address hold time High-order address set-up time High-order address hold time Memory data set-up time Memory data hold time Data set-up time Data hold time Symbol toW tAW tRW tWW tRAD tWAD tALS tALH tAHS tAHH tMS tMH tDD tDH tALH-0 toW-10 CL=50 pF Condition -- Min. 25 2toW-10 2toW-10 2toW-10 toW-10 toW-10 2toW-10 toW-10 3toW-10 toW-0 Max. -- -- -- -- toW+10 toW+10 2toW+10 toW+10 3toW+10 toW+10 -- toW-10 tALH+10 toW+10 nsec Unit
23/27
Semiconductor
MSM66589/66P589/66Q589
CLK toW toW ALE tAW PSEN tPAD AD 0-7 PC 0-7 tALS A 8-16 tAHS RD tRAD AD 0-7 RAP 0-7 tALS A 8-15 tAHS WR tWAD AD 0-7 RAP 0-7 tALS tALH tDD A 8-15 tAHS RAP 8-15 tAHH tWW DOUT 0-7 tDH tALH RAP 8-15 tAHH tRW DIN 0-7 tMS tMH tALH PC 8-16 tAPH tPW INST 0-7 tIS tIH
24/27
Semiconductor
MSM66589/66P589/66Q589
A/D CONVERTER CHARACTERISTICS (Preliminary)
(Ta=-40 to +85C, AVDD=VDD=VREF=5 V10%, AGND=GND=0 V, fOSC=20 MHz) Parameter Resolution Linearity Error Differential Linearity Error Zero Scale Error Full Scale Error Crosstalk Conversion Time Symbol n EL ED EZS EFS ECT tCONV Condition Refer to the recommended circuit. Analog input source impedance RI 5 kW tCONV=19.2 msec Refer to the measuring circuit. by ADTM set data Min. -- -- -- -- -- 6.4 Typ. -- -- -- -- -- -- - 19.2 s/CH LSB Max. 10 Unit Bit
Reference Voltage
0.1 F VREF +
-
47 W AVDD VDD +
0.1 F 47 F
+5 V
RI
0.1 47 F F
AI 0-15
+ Analog input 0.1 F
AGND
GND
0V
RI (Analog input source impedance) 5 kW
Recommended Circuit
25/27
Semiconductor
MSM66589/66P589/66Q589
- + Analog input
5 kW AI0 AI1 0.1mF
Crosstalk is defined as the difference between the A/D conversion result when applying the identical analog input to AI0 to AI15 and the A/D conversion result in the circuit in the left figure.
~
AI15
VREF or AGND
Crosstalk Measuring Circuit
Definitions of Terms
Resolution The minimum distinguishable analog input value. For 10 bits, 210=1024, i.e. (VREF-AGND) / 1024. Linearity error The variance between the ideal conversion characteristics as a 10-bit A/D converter and the actual conversion characteristics. (Quantized error is therefore not included.) In the ideal conversion, a voltage between VREF and AGND is divided into 1,024 equal steps. Differential linearity error The smoothness of the conversion. The width of analog input voltage corresponding to the change by one bit of digital output is 1 LSB=(VREF-AGND) / 1024 ideally. The variance between this ideal bit size and bit size at arbitrary point in the conversion range. Zero scale error The variance between the ideal conversion characteristics at the switching point of digital output "000H to 001H" and actual conversion characteristics. Full scale error The variance between the ideal conversion characteristics at the switching point of digital output "3FEH to 3FFH" and actual conversion characteristics.
26/27
Semiconductor
MSM66589/66P589/66Q589
PACKAGE DIMENSIONS
(Unit : mm) QFP128-P-2828-0.80-BK QFP128-P-2828-0.80-ZK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin Cu alloy Solder plating 5 mm or more 5.95 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 27/27

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